1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a semiconductor device that controls output timing of data using a latency counter. The present invention also relates to a data processing system including such a semiconductor device.
2. Description of Related Art
Synchronous memory devices represented by a synchronous DRAM (Synchronous Dynamic Random Access Memory) are widely used as a main memory or the like of personal computers. In the synchronous memory device, data is inputted and outputted in synchronism with a clock signal supplied from a controller. Thus, when a higher-speed clock signal is used, the data transfer rate can be increased.
However, because a DRAM core is consistently operated by an analog operation also in the synchronous DRAM, a considerably weak charge needs to be amplified by a sensing operation. Accordingly, it is not possible to shorten the time from issuing a read command to outputting first data. After the elapse of a predetermined delay time from the read command is issued, the first data is outputted in synchronism with an external clock signal.
This delay time is generally called “CAS latency” and is set to an integral multiple of a clock cycle. For example, in case the CAS latency is 7 (CL=7), the first data is outputted in synchronism with the external clock signal seven cycles after fetching the read command in synchronism with the external clock signal. That is, the first data is outputted after the elapse of the seven clock cycles.
Desired CAS latency is realized by the latency counter. The latency counter is a circuit that receives an internal read command MDRDT from a command decoder, and generates an internal read command DRC by delaying the command MDRDT by a period of time corresponding to the CAS latency. More specifically, the latency counter first generates an output gate signal COT, which is in synchronism with an internal clock signal LCLK supplied from a DLL circuit (phase synchronizing circuit); and an input gate signal CIT, which is generated by delaying the output gate signal COT. The output gate signal COT and the input gate signal CIT, respectively, are made up of eight-line signals; and are so configured that each line is sequentially activated for each clock cycle. When the internal read command MDRDT is supplied, the latency counter accepts the internal read command MDRDT in synchronism with the activated line signal of input gate signal CIT. Each line signal of the input gate signal CIT is associated in advance with each line signal of the output gate signal COT on a one-to-one basis. The latency counter waits until the next activation of the line signal of the output gate signal COT corresponding to the input gate signal CIT that is used to accept the internal read command MDRDT takes place. Then, in response to the activation of the output gate signal COT, the latency counter starts activating the internal read command DRC. The CAS latency is realized by the waiting period during the above process. An output circuit outputs read data to the outside in synchronization with the internal read command DRC that has become activated as described above. An example of the latency counter is disclosed in Japanese Patent Application Laid-Open No. 2011-60353.
As for a semiconductor device including a synchronous memory device, there is a semiconductor device that uses, as power source used for operating some circuits, an internal voltage that is generated by lowering an external voltage, thereby reducing power consumption. For example, there is disclosed in Japanese Patent Application Laid-Open No. 2011-60385 an example in which an internal voltage VPERI is generated from an external voltage VDD and an external voltage VSS to operate some peripheral circuits of DRAM.
However, when the internal voltage is used in a semiconductor device that uses a latency counter, there is a possibility that the margin (or latch margin of the latency counter) decreases at a time when the internal read command MDRDT is accepted in synchronism with the input gate signal CIT, and the process of accepting the internal read command MDRDT could fail as a result. The mechanism will be described below in detail.
As described above, the internal clock signal LCLK is generated by a DLL circuit. The DLL circuit is so formed as to contain a feedback circuit, which is so adjusted as to cause a delay amount equivalent to that of the output circuit, and a control circuit, which adjusts the internal clock signal LCLK in such a way that the output timing of the feedback circuit is in synchronism with an internal clock signal PreCLK, which is described later. Therefore, the phase of the internal clock signal LCLK varies according to the delay time of the feedback circuit.
Meanwhile, the internal read command MDRDT is generated by a command decoder. The command decoder receives a read command READ supplied from a command input circuit, which receives the read command READ; generates an internal read command MDRDT based on the read command READ; and then outputs the internal read command MDRDT in synchronism with an internal clock signal ICK, which is described below.
The internal clock signal PreCLK and the internal clock signal ICK, respectively, are generated as described below. That is, a clock input circuit that receives an external clock signal generates the internal clock signal PreCLK based on the external clock signal. To the DLL circuit, the internal clock signal PreCLK is supplied. The internal clock signal PreCLK is also supplied to a timing generation circuit, where the internal clock signal PreCLK is converted to an internal clock signal ICK. To the command decoder, the internal clock signal ICK is supplied.
When the internal voltage is used, among the circuits that have so far been described, the DLL circuit, the command decoder, the timing generation circuit, and the latency counter are so formed as to operate only on the internal voltage in principle in order to reduce power consumption.
By contrast, the clock input circuit and the command input circuit are so formed as to contain a circuit that operates on external voltage even when the internal voltage is used. The reason is that these circuits need to accept a signal whose amplitude value is equal to that of the external voltage from the outside. The feedback circuit in the DLL circuit also contains, as an exception, a circuit that operates on external voltage. The reason is that an output circuit that outputs read data to the outside inevitably contains a circuit that operates on external voltage.
Here, suppose that a change in external voltage has occurred. Then, a change in phase occurs at least in the following signals among the clock signals that have so far been described: the internal clock signal PreCLK and the internal clock signal LCLK. The reason is that the clock input circuit and the DLL circuit, which are used to generate the internal clock signal PreCLK and the internal clock signal LCLK, contain a circuit that operates on external voltage.
The internal clock signal PreCLK is common to the internal read command MDRDT and the input gate signal CIT. Therefore, even when a change in phase occurs, there is no effect at least on the latch margin of the latency counter. By contrast, if a change in phase of the internal clock signal LCLK occurs, a change in phase occurs only in the input gate signal CIT, and no change in phase in the internal read command MDRDT. As a result, a difference in phase occurs between the internal read command MDRDT and the input gate signal CIT, leading to a decline in the latch margin of the latency counter.
As described above, when a change in external voltage occurs, a change in phase of the input gate signal CIT occurs while the internal read command MDRDT does not change. As a result, the latch margin of the latency counter decreases. In some cases, the process of accepting the internal read command MDRDT could fail. Therefore, a technology for curbing a decline in the latch margin that is associated with a change in external voltage is desired.